Design and Optimization Approaches in Double Gate Device Architecture

According to Moore’s law, the number of transistor embedded on integrated circuit (IC) doubles approximately every two years. Thus, the size of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has to be scaled down as an increase in packing density. In current technology, the size of a transistor has shrunk below 45nm, and it has already reached its physical limit. Any attempt to shrink the MOSFET beyond this limit will expose MOSFET device to various short channel effects (SCEs) problems. Recently, however, a new architecture of MOSFET known as Double Gate MOSFET has emerged, and this will allow the IC technology continue to be shrunk while sustaining its electrical performance. Several types of Double gate MOSFET are discussed but however, the main focus is to the type of vertical DG-MOSFET. This paper will discuss about the design and optimization approaches in Double-gate (DG) MOSFET device. KeywordATHENA, ATLAS, MOSFET, Taguchi, 2k-factorial